Currently, Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing techniques generally comprise forming a metal-semiconductor compound on a source/drain region by the process of Self-Aligned Silicide (SALICIDE), in order to reduce the contact resistance between the contact and the source/drain region. However, with the rapid development of semiconductor technology, the critical dimension of devices continues to shrink and performance requirements of the devices have become increasingly higher. Hence, it is desired to use a metal of a smaller resistivity to form the metal-semiconductor compound, in order to reduce the contact resistance.
Due to the features of Nickel (Ni) and Nickel-Platinum alloy (Ni—Pt) such as low resistivity, low-temperature formation and low contact resistance, current advanced techniques commonly use Ni or Ni—Pt to form a Ni or Ni—Pt silicide by a self-aligned process.
As an example, in the case of forming a CMOS device on a silicon substrate, the self-aligned process for forming a Ni or Ni—Pt silicide comprises the steps of: depositing Ni or Ni—Pt when a gate region and a source/drain region have been formed; performing first low-temperature annealing at a temperature of about 300° C., so that the Ni or Ni—Pt on the source/drain region reacts with the silicon substrate to form a Ni-rich silicide; then removing unreacted Ni or Ni—Pt; and performing second high-temperature annealing at a temperature of about 450-500° C. so that the Ni-riched silicide are further transformed into a Ni or Ni—Pt silicide of a lower resistivity.
However, the process above for forming a Ni or Ni—Pt silicide has a problem. Due to easily diffusing of Ni and Ni—Pt, lateral diffusion of Ni or Ni—Pt occurs in the self-aligned process. As shown in FIG. 1, Ni or Ni—Pt material 120 may diffuse to a gate region 110 inside the spacer and a channel region (the region under the gate region and between source and drain regions). As a result, the formed silicide 130 may extend toward the channel region, which may severely affect performance of the device as the dimensions of the device and the dimensions of the gate and the channel decrease. For example, significant gate leakage current, connection between source and drain regions, and device reliability issues may arise.